This invention relates to amplifiers and, more particularly, to wideband monolithic integrated circuit amplifiers exhibiting high slew rates.
There are many performance characteristics which are important to users of operational amplifier circuits. Among these are gain, input and output impedance, low power consumption, bandwidth and settling time, low noise operation, common mode rejection characteristics, and amplifier input offset characteristics. It is well known that these performance characteristics are interrelated, that is, an attempt to improve a specific characteristic usually mandates acceptance of decreased performance in some other respect. Moreover, designers of silicon integrated amplifier circuits have been further constrained by the limitations of the state of the integrated circuit processing art. These constraints have resulted in a multitude of integrated operational amplifier circuits, some of which have been designed to optimize a particular operating characteristic and some of which have been designed to provide general purpose circuits which can be used in a fairly wide range of applications. In either type of design, the prior art has generally considered that the attainment of a high common mode rejection range necessitated relatively high collector-to-base bias voltages at the amplifier input stages. The use of substantial bias voltages, however, often makes level shifting stages necessary in order to maintain reasonable bias supply voltages.
In addition, although the prior art has recognized the use of feed forward techniques to enhance bandwidth and slew rate, it has been generally considered that these techniques were only applicable to amplifiers operated solely in the inverting mode. Moreover, the difficulty in economically integrating PNP transistors which exhibit good gain characteristics, especially at high frequencies, has constrained the prior art to NPN output stages or to complementary output stages which utilize laterally diffused PNP transistors. Accordingly, in the case of complementary output stages incorporating lateral PNP transistors, prior art circuits have exhibited limited bandwidth.
It is accordingly an object of this invention to realize an integrated amplifier circuit which provides high slew rate in both the inverting and noninverting modes of operation while maintaining low quiescent power consumption, low noise operation, and relatively high output signal capabilities.
It is a further object of this invention to realize an integrated amplifier circuit which has a high common mode rejection range without the use of substantial collector-to-base bias voltages and the attendant prior art level shifting stages.
It is yet another object of this invention to utilize recent advances in the art of silicon integrated circuits to provide an amplifier with a new high-speed complementary output stage which operates a low quiescent power consumption while exhibiting excellent output voltage and current capabilities.